This invention is in the field of integrated circuits, and is more specifically directed to the configuration of input/output circuits for purposes of test.
Some modern integrated circuits include functions that are configurable during or after manufacture. Typically, the configuration is defined in a non-volatile manner, so that the desired configuration is retained after power-down of the circuit. Various technologies are available for implementation of the non-volatile configuration information, including fusible links, laser-trimmable elements, and electrically erasable programmable read-only memory (EEPROM) cells. EEPROM technology has become the technology of choice for non-volatile storage of such configuration information, because of the ability to re-program that information if desired. Typically, the integrated circuit is configured by the manufacturer after the device has successfully completed functional and parametric testing. In some cases, configurability is also made available to the system user of the integrated circuit.
One example of configurable circuitry in conventional integrated circuits is logic or other functionality that selects the manner in which input and output circuitry operates. More specifically, the input/output functionality may be constructed to be operable according to a selected one of multiple protocols, each protocol conforming to the custom input/output port specifications of a particular customer or user of the device. Configurability of the selection of the protocol allows the manufacturer to produce a large quantity of the integrated circuits without regard to current demand of individual customers, and to configure the devices for a particular customer on demand.
FIG. 1a illustrates an example of an integrated circuit 2 having a configurable synchronous input/output port 6. Integrated circuit 2 includes functional circuitry 4, which performs the primary function of integrated circuit 2. Input/output port 6 is in communication with functional circuitry 4, and in the conventional manner, receives external input signals and data for processing by functional circuitry 4, and presents the results of that processing as output signals. Input/output port 6 can have various attributes. For example, input/output port 6 can be either a serial port or parallel port, can be either synchronous (receiving and presenting clocked signals) or asynchronous (receiving and presenting unclocked signals), and can communicate either via dedicated input and output terminals or via common input/output terminals (i.e., the same pins or terminals used for input and output). EEPROM 8 is provided within integrated circuit 2 to store data values that “trim” various operating parameters, for example by presenting levels on lines TRIM1, TRIM2 that adjust the output of current reference generator circuit 7 and bandgap reference circuit 9, respectively.
For the particular example of FIG. 1a, input/output port 6 is controlled in response to signals presented at enable pin EN, which is an input to port 6 that is asserted upon an external device wishing to enable the transfer of data to or from integrated circuit 2 via data pin or pins DATA. In one example, in which input/output port 6 is a serial port, the direction of the data transfer is determined by the contents of the data presented at a single data pin DATA; for example, a particular register within integrated circuit 2 may be specified by the first n bits applied to data pin DATA, with the next (n+1th bit) indicating the direction of transfer. Other approaches to control of the direction of data transfer are known in the art and may alternatively be implemented.
In this conventional integrated circuit 2, input/output port 6 can be configured according to a selected one of multiple protocols, by way of one or more programmed bits in EEPROM 8. Examples of alternative protocols available to port 6 are illustrated in FIGS. 1b and 1c. According to the protocol shown in FIG. 1b, input/output port 6 is enabled by a device external to integrated circuit 2 asserting a low level at terminal EN, followed by presenting a sequence of logic levels at terminals DATA synchronously with rising edges of a periodic clock signal at terminal CLK. The protocol shown in FIG. 1c is similar to that shown in FIG. 1b, in that an external device presents data signals on terminals DATA synchronously with rising edges of a clock signal at terminal CLK. However, in the protocol shown in FIG. 1c, the enable signal at terminal EN is active at a high logic level, rather than at a low logic level as shown in FIG. 1b. As noted above, the direction of eventual data transfer in this example is indicated by the state of a particular bit within the sequence applied to terminal or terminals DATA. The protocol according to which input/output port 6 operates is determined in response to the state of a bit within EEPROM 8. With that bit programmed in one state, input/output port 6 is configured to respond to enable signal EN at a logic low level (FIG. 1b), and in response to that bit being programmed in the opposite state, input/output port 6 is configured to respond to enable signal EN at a logic high level. In this conventional approach, the manufacturer (or possibly the user) programs that configuration bit within EEPROM 8 to select the desired protocol.
However, it is important for the manufacturer to fully test integrated circuit 2, either in wafer form or after packaging (or both), before the selection of the protocol according to which input/output port 6 will operate. In other words, in the example of FIGS. 1a through 1c, after manufacture and before configuration, the cells of EEPROM 8 can be in an indeterminate state. One cannot reliably assume the initial configuration of input/output port 6 as a result, which prevents accurate testing or characterization of integrated circuit 2.
In conventional integrated circuits, this problem is resolved by providing an external terminal by way of which the manufacturer or user, as the case may be, cam externally define the operation of the device. In the example of integrated circuit 2 of FIG. 1a, terminal TEST_CONFIG is coupled to input/output port 6. A logic level or other signal applied to terminal TEST_CONFIG defines the operating protocol of input/output port 6. Once configured by the application of this external signal, integrated circuit 2 can then be fully tested, both parametrically and functionally.
However, a separate dedicated external pin or terminal for this purpose adds substantial cost. Chip area of the integrated circuit is required for the terminal and the associated circuitry and conductor paths, even if this dedicated terminal is used only for wafer-level test. However, because small-scale integrated circuit devices may not be tested in wafer form but are instead electrically tested only after packaging, this approach requires an external package terminal to be dedicated to this test configuration function. Unfortunately, device “pin count” is a significant constraint for many integrated circuits, especially for small scale integrated circuits that the customer expects to be in a low pin count package. In addition, if an external package pin is required, the customer is typically required to bias that pin to a specified level to ensure that normal operation of the device is not disrupted, which necessitates circuit board space for routing that voltage to the dedicated external pin. From a market standpoint, it is difficult to pass this cost on to the customer for the manufacturer's benefit.